The invention relates to semiconductor memories and specifically to electrically programmable non-volatile memories, currently called EPROM; in particular, the invention relates to the manufacturing of floating gate memories.
For obtaining large-scale memories, for example memories able to store up to 16 megabits, the size of each cell of the memory has to be reduced as much as possible.
But of course, there is a limitation due to physical problems and in particular to the size of photolithographic patterns; another limitation is due to parasitic electrical parameters associated to the manufacturing process which disturb the memory operation.
Except for some proposals that have not met an industrial success, all the industrial approaches for obtaining large-scale memories correspond to a technology comprising the following main points:
an individual memory point corresponds to a MOS transistor having a floating gate made of a first polysilicon level and a control gate corresponding to a second polysilicon level;
the sources of the transistors are connected to a low potential bus Vss;
a word line for addressing a cell line is made of the second polysilicon level;
a bit line for reading the state of a cell is made of a metal (aluminum) line crossing the word lines and contacting from place to place the transistor drains;
for reducing the size of each memory point, only one contact point is provided for two adjacent drains of two transistors in a same column, this contact ensuring a connection with the bit line; also, only one contact is provided between the sources of two adjacent transistors and the bus at Vss;
the transistors are separated from each other by a thick silicon oxide (thick with respect to the transistor gate oxide), and the bit lines and the word lines pass over this thick oxide;
finally, the writing of a data in a memory cell is made in the following way: the sources of all the transistors of the memory are at a low potential Vss (for example zero volt); the word line connected to the control gate of the cell to be programmed is connected to a programmation potential Vpp (for example 15 volts), while all the other word lines are at the low potential Vss; the bit line corresponding to the point to be programmed is put at a high potential Vcc (for example 10 volts), while the bit lines of the points not to be programmed are maintained at the low potential Vss.
With such a memory architecture and the associated programmation mode, the drain of a transistor has to be electrically isolated, through a thick oxide, with respect to the drains of the adjacent transistors of the same word line. If such an isolation is not carried out, it is not possible to program a specific memory point without programming or deprogramming the other ones at the same time.
However, the thick oxide which isolates two adjacent points takes a large surface, mainly when it is obtained by a localized oxidation process (locos).
It has been suggested to replace the localized oxidation by oxide-filled grooves for reducing the total size of the cell, but this technology is not easy to implement industrially.
Structures wherein the thick oxide areas and the multiple contacts towards the drains or sources are cancelled have also been suggested. Those structures permit to reduce the size of the memory array but the addressing system gets more complex and occupies a larger surface.